This invention relates generally to memory circuits and more particularly to a timing and control circuit for generating output data bus enable and sense amp enable signals for a static random access memory circuit ("SRAM").
The basic structure of an SRAM is well known in the art to include an input address bus, a memory array constructed of rows and columns of static memory cells having inputs and outputs coupled to corresponding row and column lines. Individual memory cells are addressed by energizing appropriate row and columns line for either reading data into the selected memory cell or for reading data out onto a column line. Sense amplifiers are coupled to the column lines for sensing the small changes in charge developed on the column lines. The sense amplifiers are not always active and consuming power, but are activated by a sense amp enable signal at an appropriate time in a sequence of events necessary for reading data out of the memory. Typically, many sense amplifiers are coupled to an internal output data bus, which is also activated by a bus enable signal. The bus enable signal is usually activated slightly after the sense amp enable signal.
A basic feature of most SRAM memory circuits is an input latch to provide two modes of addressing. In a first, synchronous address mode, an input latch is activated and latches a single address signal. Subsequent received address signals are ignored and only the registered address is further processed to either write data into or read data out of a memory cell. In a second, asynchronous address mode, the input latch is transparent to the address signals. Each new address signal is processed as it is received on the input address bus. Further details of the internal structure and operation of an SRAM are set forth in the 1991 MOS DATA BOOK of MICRON TECHNOLOGY, INC. of Boise, Id. The description at pp. 4-151 through 4-164 of the data book is especially pertinent and is hereby incorporated by reference.
While the asynchronous address mode is a useful feature in many applications, where a clock edge is not available when the address is valid, for example, repeatedly changing the address signal within the normal cycle time of the memory can create problems. The memory circuit, in responding to each address signal, initiates a sequence of events such as enabling the sense amplifiers and internal output data bus, as well as precharging and equalizing internal busses, decoding row and column addresses, releasing precharge and equalization levels, and other steps necessary to read or write data into or out of the memory array. If a subsequent address signal is received too soon after an initial address is received, the sequence of events is aborted and restarted in response to the new address signal. While the subsequent address signal is processed, doing so increases noise at the output due to the unnecessary switching of internal nodes and busses, increases power dissipation due to sense amplifiers and busses being unnecessarily activated, and reduces operating speed by requiring full logic swings on the internal nodes.
Therefore, what is desired is a control and timing circuit for an SRAM placed in an asynchronous address mode to select a single address amongst several addresses received within the normal cycle time interval of the SRAM.